Deep dives into high-speed simulation, signal integrity, thermal analysis, and AI-driven EDA — written by the FlowSim engineering team.
How stackup design, via optimization, and termination strategy converge to close timing at the latest DDR5 speeds. We walk through a real board layout case study with eye diagram analysis.
Joule heating and thermally-induced signal drift are inseparable at advanced nodes. Here's how we model them together in FlowSim, and why decoupled simulation underestimates failures.
How we trained a PINN to deliver SPICE-accurate parasitics 1000× faster than full 3D field solvers, without sacrificing the physical consistency that matters for high-speed design.
Length matching, spacing, via stubs, and reference plane continuity — each has a tolerance budget at 56 Gbps. We quantify each one and show how violations compound.
Modern AI chips demand sub-milliohm PDN impedance from DC to 5 GHz. This post covers decoupling capacitor selection, plane resonance, and co-design with the package.
Via stubs create resonant notches that can shut down signal channels. We compare backdrilling and blind/buried via approaches on cost, loss, and process yield.