Understanding DDR5 Signal Integrity at 6400 MT/s

DDR5 at 6400 MT/s pushes the limits of what conventional PCB stackup design can achieve. At these data rates, a signal makes a full transition in roughly 156 ps — leaving almost no margin for reflections, crosstalk, or impedance discontinuities.

Stackup Considerations

The reference planes adjacent to the DDR5 signal layer are critical. At 6400 MT/s, a 10% impedance deviation introduces a reflected voltage of approximately 5% of the signal amplitude. In practice this means the dielectric constant (Dk) must be tightly controlled across the panel — typically requiring a core material with Dk tolerance better than ±0.1.

A typical 10-layer stackup for DDR5 places the data signals on layers 2 and 9, adjacent to solid reference planes on layers 1/3 and 8/10 respectively. This minimizes loop inductance and provides controlled 40–45 Ω single-ended impedance.

Via Optimization

Blind vias from the BGA field to the routing layer eliminate the stub resonance that plagues through-hole vias at these speeds. A 0.6 mm depth via stub creates a resonant null at approximately 42 GHz — well clear of DDR5's 3.2 GHz Nyquist. However, if through-hole vias are required for cost reasons, backdrilling to within 5 mils of the signal exit point is necessary to shift stub resonance above 20 GHz.

Termination Strategy

DDR5 uses an on-die termination (ODT) architecture with dynamic termination training. The key change from DDR4 is the addition of CA bus termination at the host side, reducing bus turnaround times. The PCB designer's responsibility is ensuring the trace length from DRAM to host is matched within ±5 ps across all data groups — typically achievable with 1–2 mil length trim routing.

Eye Diagram Analysis

FlowSim's channel simulation of this configuration shows a passing eye at 6400 MT/s with 85 mV of eye height and 0.22 UI of eye width — above the JEDEC minimum of 67 mV / 0.2 UI. The dominant jitter contributor at this speed is dielectric loss induced ISI, which accounts for 0.08 UI of the total budget.

The key takeaway: DDR5 at 6400 MT/s is achievable on standard FR-4-class materials with a disciplined stackup, careful via management, and accurate simulation-driven layout.