PDN Design for High-Current AI Accelerator Packages

Modern AI accelerator chips present some of the most demanding power delivery requirements ever seen in electronics. A flagship training chip may draw 700 W at 0.85 V — nearly 825 A of current — while requiring that the supply voltage remain within ±3% from DC through 5 GHz to maintain correct logic operation.

The Impedance Target

Achieving a flat PDN impedance profile from DC to 5 GHz requires a multi-stage decoupling strategy. The voltage regulator module (VRM) handles DC through roughly 1 MHz. Bulk capacitors on the board cover 1–10 MHz. Package capacitance handles 10–100 MHz. On-die decoupling covers 100 MHz and above.

The target impedance at each frequency is determined by the maximum allowed voltage droop divided by the maximum transient current step: Z_target = ΔV / ΔI. For a chip with 50 A transient steps and a 25 mV droop budget, Z_target = 0.5 mΩ — a stringent target that requires careful co-design of the board, package, and die.

Plane Resonance

Power and ground planes form a resonant cavity. At resonance frequencies (typically 500 MHz–3 GHz for typical package sizes), the PDN impedance can peak by 10–20 dB above the target. Embedded capacitance — thin dielectric layers of 50–100 μm between power and ground planes — provides effective damping without consuming board space.

Co-Design Workflow

FlowSim's PDN co-design workflow simulates the board, package, and die PDN together from the earliest design stage. The tool generates a frequency-domain impedance plot and automatically places decoupling capacitors to hit the target impedance profile with the minimum component count. In a recent AI accelerator project, this reduced the decoupling capacitor count by 30% while improving PDN compliance at the critical 1–100 MHz range.